1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor stacked module structure, a stacked module structure and a method for manufacturing same. More specifically, the present invention relates to a panel scale fan-out package structure in which a thin film wiring step and an assembly step are carried out on a large panel scale, and more particularly, is applicable to a semiconductor stacked module having a structure in which a plurality of packages are stacked vertically.
2. Description of the Related Art
Recent years have seen demands for higher functionality and reduced size and weight in electronic equipment, and accordingly, progress has been made in the high-density integration of electronic components and also in high-density mounting, and semiconductor devices used in such electronic equipment have also been becoming increasingly compact in size more than before.
As a method for manufacturing a semiconductor device such as an LSI unit or an IC module, firstly, a plurality of semiconductor elements judged to be good quality by an electrical properties test are arranged and bonded in a prescribed configuration on a supporting plate, with the element circuit surface facing downwards, whereupon, for instance, a resin sheet is arranged thereon and molded by applying heat and pressure, thereby sealing the plurality of semiconductor elements in a lump, whereupon the supporting plate is peeled away, the resin sealed body is cut and machined to a prescribed shape (for example, a circular shape), an insulating material layer is formed on the element circuit surfaces of the semiconductor elements buried in the sealed resin body, openings are formed in accordance with the positions of the electrode pads of semiconductor elements on the insulating material layer, and a wiring layer is then formed on top of the insulating material layer, in addition to which conducting sections (via sections) connected to the electrode pads of the semiconductor elements are formed inside the openings, whereupon a solder resist layer is formed, solder balls, which are to be external electrode terminals, are formed successively, and each semiconductor element is then cut out individually, one by one, to complete the semiconductor devices (for example, see Japanese Patent Publication No. 2003-197662).
However, in a conventional semiconductor device obtained in this way, when sealing with resin the plurality of semiconductor elements all together, the resin contracts upon curing and since the amount of contraction does not necessarily comply with the design, the positions after curing of the resin may deviate from the design positions, depending on the arrangement positions of the semiconductor elements, and in the semiconductor elements having positional deviation of this kind, positional deviation occurs between the via sections formed in the openings of the insulating material layer and the electrode pads of the semiconductor elements, and hence there is a problem in that connection reliability declines.
A semiconductor device which resolves this problem is described in Japanese Patent Publication No. 2010-219489.
FIG. 8 shows the basic structure of this device.
The semiconductor device 30 comprises a flat plate 31 constituted by a cured resin body or metal, a semiconductor element 32 being disposed with an element circuit surface facing upwards, on one main surface of the flat plate 31, and the surface on the opposite side to the element circuit surface (rear surface) being fixed to the flat plate 31 by adhesive 33. Only one insulating material layer 34 is formed on whole of the main surface of the flat plate 31 so as to cover the element circuit surface of the semiconductor element 32. A wiring layer 35 made from a conductive metal, such as copper, is formed on top of this single insulating material layer 34, and one portion thereof is extracted to a peripheral region of the semiconductor element 32. Furthermore, a via section 36 which electrically connects an electrode pad (not illustrated) of the semiconductor element 32 and the wiring layer 35 is formed on the insulating material layer 34 formed on top of the element circuit surface of the semiconductor element 32. This via section 36 is formed in an integrated fashion, together with the wiring layer 35. Moreover, a plurality of solder balls 37 which are external electrodes are formed at prescribed positions on the wiring layer 35. Furthermore, a protective layer such as a solder resist layer 38 is formed on top of the insulating material layer 34, and on top of the wiring layer 35 apart from the junctions with the solder balls 37.
The semiconductor device according to Japanese Patent Publication No. 2010-219489 has high connection reliability between the electrodes of the semiconductor element and the wiring layer, by means of the composition described above, and enables a semiconductor device which is compatible with miniaturization of the electrodes to be obtained inexpensively with a high yield rate.
However, with the semiconductor device described in Japanese Patent Publication No. 2010-219489, it is difficult to provide vias which pass through the package from the front side to the rear side thereof, and therefore it has been impossible to apply to stacked modules having a three-dimensional structure, which have been expanding rapidly in recent years and in which a semiconductor package or circuit substrate is stacked on another semiconductor package.
According to recent trends, there have been demands for further reduction in semiconductor package size and increase in the number of mounted semiconductor elements, and in response to these demands, a semiconductor apparatus having a package on package (POP) structure (Japanese Patent Publication No. 2008-218505), and a semiconductor apparatus having a through silicon via (TSV) structure (Japanese Patent Publication No. 2010-278334) have been proposed and developed, in which a semiconductor package or circuit substrate is stacked on another semiconductor package.
A semiconductor device having a conventional POP structure is now described on the basis of FIG. 9. The package on package (POP) is a package format in which a plurality of different LSIs are respectively assembled in individual packages, and after testing, these packages are stacked together.
A semiconductor device 40 is formed by stacking one semiconductor package 42 on another semiconductor package 41. A semiconductor element 44 is mounted on top of the substrate 43 of the lower-side semiconductor package 41, and an electrode pad (not illustrated) formed in a peripheral portion of the semiconductor element 44, and an electrode pad 45 on the substrate are electrically connected by a wire 46. The whole surface of the semiconductor element 44 is sealed with a sealing member 47. The semiconductor package 41 and the semiconductor package 42 are electrically connected to each other by reflow via an external connection terminal 48 (solder ball) formed on the lower surface of the semiconductor package 42.
A POP structure has advantages in that a larger mounting surface area can be ensured when mounting equipment, by stacking a plurality of packages as described above, and furthermore, production losses can be reduced since the respective packages can be tested individually. However, since the POP structure is formed by assembling packages individually and stacking these individually assembled packages, then it is difficult to reduce assembly costs by reducing (shrinking) the size of the semiconductor elements, and the assembly costs of the stacked module are very high indeed.
Next, a semiconductor device having a conventional TSV structure will be described with reference to FIG. 10. As shown in FIG. 10, the semiconductor device 50 has a structure in which a plurality of semiconductor elements 51, each having the same function and structure and each manufactured using the same manufacturing mask, and one interposer substrate 52, are stacked via a resin layer 53. The semiconductor element 51 is a semiconductor element using a silicon substrate, which is connected electrically to semiconductor elements adjacent thereabove and therebelow by a plurality of through electrodes (TSV: through silicon via) 54 passing through the silicon substrate, and furthermore is sealed by a sealing resin 55. On the other hand, the interposer substrate 52 is a circuit substrate made of resin and a plurality of external connection terminals (solder balls) 56 are formed on the rear surface thereof.
In a conventional through silicon via (TSV) stacked module structure, there is a possibility that the semiconductor element may be damaged due to the provision of through holes in each of the individual semiconductor elements, and it is necessary to add a plurality of complicated and expensive wafer steps, such as a step for forming via electrodes inside the through holes, thus leading to significant cost increases for the overall vertical stacked module. Furthermore, with a conventional structure, it has been difficult to achieve stacked mounting including chips of different sizes, and due to the “provision of a different rewiring layer for each layer” which is essential when stacking the same chips such as in a memory, the manufacturing costs are much higher than in a normal memory module, and there has been a problem in that price reduction due to the effects of mass production is not expected to a great extent.